Journal of information and
communication convergence engineering
(J. Inf. Commun. Converg. Eng.)

As an extension of Moore’s law, three-dimensional (3D) integrated circuits (3DICs), which vertically stack multiple active layers, have been studied [1]. Among the various 3DIC technologies, monolithic 3DIC (M3DIC) [2-4], which sequentially fabricates multiple active layers with monolithic inter-tier-vias (MIVs), has power, performance, and cost advantages in comparison to 3DICs based on through-silicon-via (TSV) [5]. Owing to the success of low-temperature processes such as CoolCube TM integration [6] for top-tier transistors in M3DIC, the performance of bottom-tier transistors is less degraded, and thus M3DIC enables nanoscale MIV to be used for connecting vertical transistor/circuit layers [7-10]. To solve the difficulties in filling a high-aspect-ratio MIV, increasing the power density, and reducing the RC delay, a thin interlayer dielectric (ILD) between stacked transistors is created [11]. The electrical coupling between stacked transistors has been investigated because the change in the gate voltage of the bottom-tier transistor affects the current of the top-tier transistor owing to the thinned ILD [12-14].

In 2D planar logic gates, the inverter structure is used as a basic unit cell for the standard cells. In a standard cell, all n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs) or p-type MOSFETs are at one level, where a drain or source is commonly applied. All standard cells are equal in height and can easily fit into a standard row of cells. It is well known that the standard cell layout of a 2D planar logic gate reduces the cell area and makes it easy for the automatic place and route (APR) tool to place and route them [15]. Fig. 1(a) shows a cross-sectional view of a previously reported M3D-NAND gate consisting of a monolithic 3D (M3D) inverter (M3D-INV) used as a basic unit cell, similar to a 2D standard cell [7-9, 12-14]. Because the M3D-NAND gate shares the drain or source regions in top- or bottom-tier transistors, its area and RC delay may be reduced in comparison to those of the NAND gate in which an M3D-INV is used as a basic unit cell and then constructed using interconnects such as metal lines (MLs) or MIVs between M3D-INVs. However, because each standard cell must be designed with its own layout as an example of an M3D-NAND, it requires its own mask. Without designing all layouts of the logic gates separately, only one building block (unit cell), such as an M3D-INV, is needed; thus, one mask is required, which can be uniformly placed by arranging the cells throughout, as shown in Fig. 1(b), and the placed cells can be routed using the interconnects. It is necessary to compare the two types of 3D standard cell methods in terms of their area, power, and delay. In addition, in two types of M3DIC 3D standard cells, the electrical coupling between transistors stacked in an M3D-INV needs to be efficiently simulated and designed for achieving digital logic.

Figure 1. Cross-section of M3D-NAND: (a) previous [8] and (b) proposed versions consisting of modularized inverters.

In this study, various types of logic circuits consisting only of M3D-INVs and connected with interconnects are proposed. In Section II, two types of standard M3D-NAND cell are compared in terms of area, power, and delay. In Section III, the performances of various types of logic circuits consisting of the proposed M3D-INV unit cell are compared according to the thickness of the ILD (T_ILD). Finally, in Section IV, some concluding remarks are provided.

In this section, the previous and proposed M3D-NAND and M3D-NOR gates are compared with results simulated using the technology computer-aided design (TCAD) simulator ATLAS [16].

Fig. 1(a) shows a cross-section of the M3D-NAND gate, similar to a 2D standard cell, which was designed to minimize the area in previous studies [12]. Fig. 1(b) shows a cross section of the NAND gate designed using modularized M3D-INVs, as demonstrated in this study. The top and bottom tiers consist of an n-MOSFET and a p-MOSFET, respectively. The M3D-NAND gate consists of two modularized inverters. The doping concentrations of the source, drain, lightly doped drain (LDD), and channel of the MOSFETs were 10²¹, 10¹⁸, and 10¹⁵ cm^-3, respectively. The gate length, gate oxide thickness, and T_ILD of the MOSFETs were 30, 1, and 10 nm, respectively. In addition, SiO₂ was used as the gate oxide and ILD. According to the generally used design rule, the distance between the modularized inverters is 50 nm.

Figs. 2(a) and (c) show the structures of the proposed and previous M3D-NAND gates, respectively. The proposed M3D-NAND gates consist of two modularized unit cell M3D-INVs. Figs. 2(b) and (d) show the 2D layouts of the proposed and previous M3D-NAND gates, respectively. The external parasitic capacitances of the M3D-NAND gates shown in Figs. 2(a) and (c) from the MLs, vias, and contacts were extracted using a TCAD simulator [16, 17] and are listed in Table 1, where T_ILD is divided into 10 and 100 nm units to investigate the electrical coupling effects between stacked transistors.

Table 1 . Extracted capacitance of M3D-NAND.

Capacit ance	TILD [nm]		Capacit ance	TILD [nm]
	10	100		10	100
	Values [aF]			Values [aF]
CgBns	3.44	4.23	CgAns	3.47	4.32
CgBd	292.2	310.40	CgAnd	9.27	10.23
CgBps	1.42	1.42	CgAps	0.40	0.40
Cnsd	1.66	1.94	Cpsd	0.32	0.35
Cnsps	0.71	0.09	Ccd	0.98	1.00
CgBc	1.35	1.31	CgAc	2.09	2.09
Cnsc	0.80	0.87	Cpsc	0.79	0.77

Figure 2. (a) Proposed M3D-NAND, (b) 2D layout of proposed M3D-NAND, (c) previous M3D-NAND, and (d) 2D layout of previous M3D-NAND.

Figs. 3(a) and (c) show the structures of the proposed and previous M3D-NOR gates, respectively. The proposed M3D-NOR gates consist of two modularized unit-cell M3D-INVs. Figs. 3(b) and (d) show the 2D layouts of the proposed and previous M3D-NOR gates, respectively. The external parasitic capacitances of the M3D-NOR gates, shown in Figs. 3(a) and (c), from the MLs, vias, and contacts were extracted using the TCAD simulator and are listed in Table 2 for T_ILD = 10 and 100 nm.

Table 2 . Extracted capacitance of M3D-NOR.

Capacit ance	TILD [nm]		Capacit ance	TILD [nm]
	10	100		10	100
	Values [aF]			Values [aF]
CgBns	1.26	13.48	CgAns	1.79	17.95
CgBd	17.30	10.31	CgAnd	142.70	142.72
CgBps	2.78	40.37	CgAps	7.50	0.65
Cnsd	2.42	24.20	Cpsd	3.50	3.22
Cnsps	36.50	0.19	Ccd	7.20	7.00
CgBc	2.89	36.20	CgAc	37.50	37.41
Cnsc	7.80	7.54	Cpsc	8.90	4.37

Figure 3. (a) Proposed M3D-NOR, (b) 2D layout of proposed M3D-NOR, (c) previous M3D-NOR, and (d) 2D layout of previous M3D-NOR.

Figs. 4(a) and (b) show the voltage transfer characteristics (VTCs) and transient responses of the two types of M3D-NAND with T_ILD = 10 nm, respectively. The M3D-NANDs neglect the MIVs and MLs, as shown in Figs. 2(a) and (c). In Fig. 4(a), the red and blue dotted triangles denote the VTCs of the proposed and previous M3D-NAND gates when V_B = 1 V (high level), respectively, and the black lines and symbols denote the VTCs of the proposed and previous M3D-NAND gates when V_B = 0 V (low level). The VTCs of the proposed M3D-NAND reproduce those of the previous version well. In Fig. 4(b), the black, red, blue, and red lines denote the inputs V_IN,A and V_IN,B, output V_out of the proposed M3D-NAND, and output V_out of the previous M3D-NAND, respectively. The extracted propagation delay (t_p), falling time (t_f), and rising time (t_r) of the proposed M3D-NAND increased by 16.4%, 36.1%, and 11.8%, respectively, compared to those of the previous M3D-NAND.

Figure 4. M3D-NAND gate neglecting external parasitic capacitances: (a) VTCs and (b) transient response.

In this section, the simulation results of the previous and proposed M3D logics are described using the Simulation Program with Integrated Circuit Emphasis (SPICE) with the extracted parameters of the LETI-UTSOI MOSFET (version 2.1) model for NMOS and PMOS [18], and the extracted external capacitances shown in Tables 1 and 2. The M3D logic considers MIVs and MLs, as shown in Figs. 2 and 3. The area, propagation delay, and power consumption of M3D logic, such as the buffer, NAND, NOR, 2 ´ 1 multiplexer (MUX), and D flip-flop are compared for two cases (T_ILD = 10 and 100 nm) with and without an electrical coupling between the stacked devices.

Figs. 5(a)-(d) show the transient response of the M3D-NAND, M3D-NOR, M3D 2 × 1 MUX, and M3D D flip-flop, respectively. In Figs. 5(a)-(c), the black and red lines denote the inputs V_IN,A and V_IN,B, respectively. In Fig. 5(c), the orange line denotes the selection line V_sel for the M3D 2 ´ 1 MUX. In Fig. 5(d), the black and red lines denote clock V_Clk and input V_D of the M3D D flip-flop, respectively. The blue and green lines denote the output V_outs for T_ILD = 10 and 100 nm, respectively.

Figure 5. Transient response. (a) M3D-NAND gate, (b) M3D-NOR gate, (c) M3D 2x1 MUX, (d) M3D D flip-flop.

Tables 3-5 show the area, propagation delay (t_p), rising time (t_r), falling time (t_f), static power consumption, and dynamic power consumption of the M3D-NAND, M3D-NOR, and three logics of the M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop, respectively. In the case of T_ILD = 10 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 12%, 15%, 11%, 0%, and 11%, respectively, compared with those of the previous versions. In the case of T_ILD = 100 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 19%, 13%, 10%, 0%, and 19% compared to those of previous versions, respectively. The average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop are the same as those of the previous versions because both consist of modularized M3DINVs. The propagation delay, rising time, falling time, and dynamic power of the proposed M3D logic with T_ILD = 10 nm increased by 15%, 13%, 14%, and 32% in comparison to those with T_ILD = 100 nm, respectively. The static power of the proposed M3D logic with T_ILD = 10 nm decreased by 65% compared to that with T_ILD = 100 nm because the leakage current of the top-tier transistor in M3D logic with T_ILD = 10 nm is lower than that with T_ILD = 100 nm owing to the stronger coupling under T_ILD = 10 nm [12].

Table 3 . Performance of M3D-NAND gate.

Performance	Previous		Proposed
	TILD [nm]
	10	100	10	100
Area [nm2]	0.12	0.12	0.16	0.16
Propagation delay [ps]	5.83	4.98	6.72	6.22
Rising time [ps]	6.54	6.40	8.25	7.65
Failing time [ps]	7.62	7.43	9.06	8.47
Static power [nW]	01.9	3.97	1.9	3.97
Dynamic power [μW]	15.2	12.1	17.0	14.3

Table 4 . Performance of M3D-NOR gate.

Performance	Previous		Proposed
	TILD [nm]
	10	100	10	100
Area [nm2]	0.12	0.12	0.16	0.16
Propagation delay [ps]	5.66	4.66	6.14	5.25
Rising time [ps]	13.2	11.4	13.8	12.2
Failing time [ps]	2.52	2.23	2.61	2.38
Static power [nW]	9.78	37.9	9.78	37.9
Dynamic power [μW]	15.4	12.0	17.0	14.3

Table 5 . Performance of M3D-buffer, 2x1 MUX, and D flip-flop.

Performance	M3D-Buffer		M3D 2x1 MUXM3D D flip-flop
	TILD [nm]
	10	100	10	100	10	100
Area [nm2]	0.16	0.16	0.25	0.25	0.49	0.49
Propagation delay [ps]	8.06	6.19	3.81	3.27	162.0	158.5
Rising time [ps]	8.25	7.90	7.29	6.02	7.95	6.80
Failing time [ps]	5.90	5.44	5.95	4.87	6.26	5.10
Static power [nW]	10.1	24.1	4.89	18.9	19.8	61.2
Dynamic power [μW]	35.8	27.2	3.61	2.74	9.42	5.98

In this study, various types of M3D logic circuits consisting only of modularized M3D-INVs and their interconnects were proposed. The proposed M3D logics were compared with previous M3D logics using TCAD and SPICE simulations. The DC characteristics of the previous and proposed M3D logic systems are almost the same. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. In particular, the average area of the proposed M3D NAND and NOR increased by approximately 37% compared with the previous versions. Although the proposed M3D logic has the disadvantages of a larger space and lower performance than the previous cases, it can be easily designed using a single modularized M3D-INV without designing all layouts of the logic gates separately. The proposed M3D logic gates may be less sensitive to process variations, such as a random dopant fluctuation (RDF) and work function variation because there is no common region between transistors in the logic gates and because the transistors are separated inside their logics. To compare the electrical coupling between the stacked devices in the previous and proposed M3D logic, two cases of T_ILD = 10 and 100 nm were simulated. The delay and dynamic power consumption of both M3D logics at T_ILD = 100 nm, in which electrical coupling can be neglected, are faster and lower, respectively, than those at T_ILD = 10 nm, in which electrical coupling must be considered.

This research was supported by the Basic Science Research Program through the NRF of Korea, funded by the Ministry of Education (NRF-2019R1A2C1085295). This study was also supported by the IDEC (EDA tool).