Journal of information and communication convergence engineering 2022; 20(2): 137-142

Published online June 30, 2022

https://doi.org/10.6109/jicce.2022.20.2.137

© Korea Institute of Information and Communication Engineering

Investigation into Electrical Characteristics of Logic Circuit Consisting of Modularized Monolithic 3D Inverter Unit Cell

Geun Jae Lee1, Tae Jun Ahn2, Sung Kyu Lim3, and Yun Seop Yu1,2* , KIICE

1ICT & Robotics Engineering and IITC, Hankyong National University, Anseong 17579, Republic of Korea
2Department of Electrical, Electronic, and Control Engineering, Hankyong National University, Anseong 17579, Republic of Korea
3School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta 30332, USA

Correspondence to : Yun Seop Yu (E-mail: ysyu@hknu.ac.kr, Tel: +82-670-5293)
Department of Electrical, Electronic, and Control Engineering, Hankyong National University, Anseong 17579, Republic of Korea.

Received: November 5, 2021; Revised: December 1, 2021; Accepted: December 9, 2021

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

Keywords Monolithic 3D Integrated-Circuit, Modularized Inverter Cell, Standard cell library, Interconnects

As an extension of Moore’s law, three-dimensional (3D) integrated circuits (3DICs), which vertically stack multiple active layers, have been studied [1]. Among the various 3DIC technologies, monolithic 3DIC (M3DIC) [2-4], which sequentially fabricates multiple active layers with monolithic inter-tier-vias (MIVs), has power, performance, and cost advantages in comparison to 3DICs based on through-silicon-via (TSV) [5]. Owing to the success of low-temperature processes such as CoolCube TM integration [6] for top-tier transistors in M3DIC, the performance of bottom-tier transistors is less degraded, and thus M3DIC enables nanoscale MIV to be used for connecting vertical transistor/circuit layers [7-10]. To solve the difficulties in filling a high-aspect-ratio MIV, increasing the power density, and reducing the RC delay, a thin interlayer dielectric (ILD) between stacked transistors is created [11]. The electrical coupling between stacked transistors has been investigated because the change in the gate voltage of the bottom-tier transistor affects the current of the top-tier transistor owing to the thinned ILD [12-14].

In 2D planar logic gates, the inverter structure is used as a basic unit cell for the standard cells. In a standard cell, all n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs) or p-type MOSFETs are at one level, where a drain or source is commonly applied. All standard cells are equal in height and can easily fit into a standard row of cells. It is well known that the standard cell layout of a 2D planar logic gate reduces the cell area and makes it easy for the automatic place and route (APR) tool to place and route them [15]. Fig. 1(a) shows a cross-sectional view of a previously reported M3D-NAND gate consisting of a monolithic 3D (M3D) inverter (M3D-INV) used as a basic unit cell, similar to a 2D standard cell [7-9, 12-14]. Because the M3D-NAND gate shares the drain or source regions in top- or bottom-tier transistors, its area and RC delay may be reduced in comparison to those of the NAND gate in which an M3D-INV is used as a basic unit cell and then constructed using interconnects such as metal lines (MLs) or MIVs between M3D-INVs. However, because each standard cell must be designed with its own layout as an example of an M3D-NAND, it requires its own mask. Without designing all layouts of the logic gates separately, only one building block (unit cell), such as an M3D-INV, is needed; thus, one mask is required, which can be uniformly placed by arranging the cells throughout, as shown in Fig. 1(b), and the placed cells can be routed using the interconnects. It is necessary to compare the two types of 3D standard cell methods in terms of their area, power, and delay. In addition, in two types of M3DIC 3D standard cells, the electrical coupling between transistors stacked in an M3D-INV needs to be efficiently simulated and designed for achieving digital logic.

Fig. 1. Cross-section of M3D-NAND: (a) previous [8] and (b) proposed versions consisting of modularized inverters.

In this study, various types of logic circuits consisting only of M3D-INVs and connected with interconnects are proposed. In Section II, two types of standard M3D-NAND cell are compared in terms of area, power, and delay. In Section III, the performances of various types of logic circuits consisting of the proposed M3D-INV unit cell are compared according to the thickness of the ILD (TILD). Finally, in Section IV, some concluding remarks are provided.

In this section, the previous and proposed M3D-NAND and M3D-NOR gates are compared with results simulated using the technology computer-aided design (TCAD) simulator ATLAS [16].

Fig. 1(a) shows a cross-section of the M3D-NAND gate, similar to a 2D standard cell, which was designed to minimize the area in previous studies [12]. Fig. 1(b) shows a cross section of the NAND gate designed using modularized M3D-INVs, as demonstrated in this study. The top and bottom tiers consist of an n-MOSFET and a p-MOSFET, respectively. The M3D-NAND gate consists of two modularized inverters. The doping concentrations of the source, drain, lightly doped drain (LDD), and channel of the MOSFETs were 1021, 1018, and 1015 cm-3, respectively. The gate length, gate oxide thickness, and TILD of the MOSFETs were 30, 1, and 10 nm, respectively. In addition, SiO2 was used as the gate oxide and ILD. According to the generally used design rule, the distance between the modularized inverters is 50 nm.

Figs. 2(a) and (c) show the structures of the proposed and previous M3D-NAND gates, respectively. The proposed M3D-NAND gates consist of two modularized unit cell M3D-INVs. Figs. 2(b) and (d) show the 2D layouts of the proposed and previous M3D-NAND gates, respectively. The external parasitic capacitances of the M3D-NAND gates shown in Figs. 2(a) and (c) from the MLs, vias, and contacts were extracted using a TCAD simulator [16, 17] and are listed in Table 1, where TILD is divided into 10 and 100 nm units to investigate the electrical coupling effects between stacked transistors.

Table 1 . Extracted capacitance of M3D-NAND

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns3.444.23CgAns3.474.32
CgBd292.2310.40CgAnd9.2710.23
CgBps1.421.42CgAps0.400.40
Cnsd1.661.94Cpsd0.320.35
Cnsps0.710.09Ccd0.981.00
CgBc1.351.31CgAc2.092.09
Cnsc0.800.87Cpsc0.790.77


Fig. 2. (a) Proposed M3D-NAND, (b) 2D layout of proposed M3D-NAND, (c) previous M3D-NAND, and (d) 2D layout of previous M3D-NAND.

Figs. 3(a) and (c) show the structures of the proposed and previous M3D-NOR gates, respectively. The proposed M3D-NOR gates consist of two modularized unit-cell M3D-INVs. Figs. 3(b) and (d) show the 2D layouts of the proposed and previous M3D-NOR gates, respectively. The external parasitic capacitances of the M3D-NOR gates, shown in Figs. 3(a) and (c), from the MLs, vias, and contacts were extracted using the TCAD simulator and are listed in Table 2 for TILD = 10 and 100 nm.

Table 2 . Extracted capacitance of M3D-NOR

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns1.2613.48CgAns1.7917.95
CgBd17.3010.31CgAnd142.70142.72
CgBps2.7840.37CgAps7.500.65
Cnsd2.4224.20Cpsd3.503.22
Cnsps36.500.19Ccd7.207.00
CgBc2.8936.20CgAc37.5037.41
Cnsc7.807.54Cpsc8.904.37


Fig. 3. (a) Proposed M3D-NOR, (b) 2D layout of proposed M3D-NOR, (c) previous M3D-NOR, and (d) 2D layout of previous M3D-NOR.

Figs. 4(a) and (b) show the voltage transfer characteristics (VTCs) and transient responses of the two types of M3D-NAND with TILD = 10 nm, respectively. The M3D-NANDs neglect the MIVs and MLs, as shown in Figs. 2(a) and (c). In Fig. 4(a), the red and blue dotted triangles denote the VTCs of the proposed and previous M3D-NAND gates when VB = 1 V (high level), respectively, and the black lines and symbols denote the VTCs of the proposed and previous M3D-NAND gates when VB = 0 V (low level). The VTCs of the proposed M3D-NAND reproduce those of the previous version well. In Fig. 4(b), the black, red, blue, and red lines denote the inputs VIN,A and VIN,B, output Vout of the proposed M3D-NAND, and output Vout of the previous M3D-NAND, respectively. The extracted propagation delay (tp), falling time (tf), and rising time (tr) of the proposed M3D-NAND increased by 16.4%, 36.1%, and 11.8%, respectively, compared to those of the previous M3D-NAND.

Fig. 4. M3D-NAND gate neglecting external parasitic capacitances: (a) VTCs and (b) transient response.

In this section, the simulation results of the previous and proposed M3D logics are described using the Simulation Program with Integrated Circuit Emphasis (SPICE) with the extracted parameters of the LETI-UTSOI MOSFET (version 2.1) model for NMOS and PMOS [18], and the extracted external capacitances shown in Tables 1 and 2. The M3D logic considers MIVs and MLs, as shown in Figs. 2 and 3. The area, propagation delay, and power consumption of M3D logic, such as the buffer, NAND, NOR, 2 ´ 1 multiplexer (MUX), and D flip-flop are compared for two cases (TILD = 10 and 100 nm) with and without an electrical coupling between the stacked devices.

Figs. 5(a)-(d) show the transient response of the M3D-NAND, M3D-NOR, M3D 2 × 1 MUX, and M3D D flip-flop, respectively. In Figs. 5(a)-(c), the black and red lines denote the inputs VIN,A and VIN,B, respectively. In Fig. 5(c), the orange line denotes the selection line Vsel for the M3D 2 ´ 1 MUX. In Fig. 5(d), the black and red lines denote clock VClk and input VD of the M3D D flip-flop, respectively. The blue and green lines denote the output Vouts for TILD = 10 and 100 nm, respectively.

Fig. 5. Transient response. (a) M3D-NAND gate, (b) M3D-NOR gate, (c) M3D 2x1 MUX, (d) M3D D flip-flop.

Tables 3-5 show the area, propagation delay (tp), rising time (tr), falling time (tf), static power consumption, and dynamic power consumption of the M3D-NAND, M3D-NOR, and three logics of the M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop, respectively. In the case of TILD = 10 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 12%, 15%, 11%, 0%, and 11%, respectively, compared with those of the previous versions. In the case of TILD = 100 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 19%, 13%, 10%, 0%, and 19% compared to those of previous versions, respectively. The average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop are the same as those of the previous versions because both consist of modularized M3DINVs. The propagation delay, rising time, falling time, and dynamic power of the proposed M3D logic with TILD = 10 nm increased by 15%, 13%, 14%, and 32% in comparison to those with TILD = 100 nm, respectively. The static power of the proposed M3D logic with TILD = 10 nm decreased by 65% compared to that with TILD = 100 nm because the leakage current of the top-tier transistor in M3D logic with TILD = 10 nm is lower than that with TILD = 100 nm owing to the stronger coupling under TILD = 10 nm [12].

Table 3 . Performance of M3D-NAND gate

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.834.986.726.22
Rising time [ps]6.546.408.257.65
Failing time [ps]7.627.439.068.47
Static power [nW]01.93.971.93.97
Dynamic power [μW]15.212.117.014.3


Table 4 . Performance of M3D-NOR gate

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.664.666.145.25
Rising time [ps]13.211.413.812.2
Failing time [ps]2.522.232.612.38
Static power [nW]9.7837.99.7837.9
Dynamic power [μW]15.412.017.014.3


Table 5 . Performance of M3D-buffer, 2x1 MUX, and D flip-flop

PerformanceM3D-BufferM3D 2x1 MUXM3D D flip-flop
TILD [nm]
101001010010100
Area [nm2]0.160.160.250.250.490.49
Propagation delay [ps]8.066.193.813.27162.0158.5
Rising time [ps]8.257.907.296.027.956.80
Failing time [ps]5.905.445.954.876.265.10
Static power [nW]10.124.14.8918.919.861.2
Dynamic power [μW]35.827.23.612.749.425.98

In this study, various types of M3D logic circuits consisting only of modularized M3D-INVs and their interconnects were proposed. The proposed M3D logics were compared with previous M3D logics using TCAD and SPICE simulations. The DC characteristics of the previous and proposed M3D logic systems are almost the same. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. In particular, the average area of the proposed M3D NAND and NOR increased by approximately 37% compared with the previous versions. Although the proposed M3D logic has the disadvantages of a larger space and lower performance than the previous cases, it can be easily designed using a single modularized M3D-INV without designing all layouts of the logic gates separately. The proposed M3D logic gates may be less sensitive to process variations, such as a random dopant fluctuation (RDF) and work function variation because there is no common region between transistors in the logic gates and because the transistors are separated inside their logics. To compare the electrical coupling between the stacked devices in the previous and proposed M3D logic, two cases of TILD = 10 and 100 nm were simulated. The delay and dynamic power consumption of both M3D logics at TILD = 100 nm, in which electrical coupling can be neglected, are faster and lower, respectively, than those at TILD = 10 nm, in which electrical coupling must be considered.

This research was supported by the Basic Science Research Program through the NRF of Korea, funded by the Ministry of Education (NRF-2019R1A2C1085295). This study was also supported by the IDEC (EDA tool).

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Geun Jae Lee

received his BS from the Department of Electrical, Electronic, and Control Engineering, Hankyong National University, Anseong, Republic of Korea, in 2020. He is currently an MS student at the Department of ICT and Robotics Engineering, Hankyong National University. His research is focused on monolithic 3D integrated-circuits, steep switching devices, and memory devices.


Tae Jun Ahn

received a BS in electronics engineering in 2016 and an MS in electrical, electronic, and control engineering in 2018 from Hankyong National University, Anseong, Korea, respectively. He is currently pursuing his PhD in electrical, electronic, and control engineering from Hankyong National University, Anseong, Republic of Korea. His research interests modeling, simulation, and optimization of next-generation devices for monolithic 3D ICs.


Sung Kyu Lim

received his BS and MS degrees and his PhD from the Computer Science Department, University of California, Los Angeles, USA in 1994, 1997, and 2000, respectively. He is a full professor at the School of Electrical and Computer Engineering, Georgia Institute of Technology, USA. His research focus is on the architecture, design, and testing of and EDA solutions for 3D ICs. His research on 3D IC reliability was featured as a Research Highlight in Communications of the ACM in 2014. Dr. Lim received the National Science Foundation Faculty Early Career Development (CAREER) Award in 2006. His work was also nominated for the Best Paper award at ISPD’06, ICCAD’09, CICC’10, DAC’11, DAC’12, ISLPED’12, and DAC’14. He is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.


Yun Seop Yu

received his BS and MS degrees and his PhD from the Department of Electronics Engineering, Korea University, Seoul, Republic of Korea in 1995, 1997, and 2001, respectively. From 2001 to 2002, he worked as a guest researcher at the Electronics and Electrical Engineering Laboratory, NIST, Gaithersburg, MD. From 2014 to 2015, he worked as a visiting scholar at the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA. He is full professor in the School of ICT, Robotics, and Mechanical Engineering, Hankyong National University, Anseong, Republic of Korea. His main research interests are in the fields of modeling various nano devices for efficient circuit simulation, and future memory, logic, and sensor designs using these devices. He is also interested in the fabrication and characterization of various nano devices. He has authored and coauthored 60 international refereed journal papers.


Article

Journal of information and communication convergence engineering 2022; 20(2): 137-142

Published online June 30, 2022 https://doi.org/10.6109/jicce.2022.20.2.137

Copyright © Korea Institute of Information and Communication Engineering.

Investigation into Electrical Characteristics of Logic Circuit Consisting of Modularized Monolithic 3D Inverter Unit Cell

Geun Jae Lee1, Tae Jun Ahn2, Sung Kyu Lim3, and Yun Seop Yu1,2* , KIICE

1ICT & Robotics Engineering and IITC, Hankyong National University, Anseong 17579, Republic of Korea
2Department of Electrical, Electronic, and Control Engineering, Hankyong National University, Anseong 17579, Republic of Korea
3School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta 30332, USA

Correspondence to:Yun Seop Yu (E-mail: ysyu@hknu.ac.kr, Tel: +82-670-5293)
Department of Electrical, Electronic, and Control Engineering, Hankyong National University, Anseong 17579, Republic of Korea.

Received: November 5, 2021; Revised: December 1, 2021; Accepted: December 9, 2021

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

Keywords: Monolithic 3D Integrated-Circuit, Modularized Inverter Cell, Standard cell library, Interconnects

I. INTRODUCTION

As an extension of Moore’s law, three-dimensional (3D) integrated circuits (3DICs), which vertically stack multiple active layers, have been studied [1]. Among the various 3DIC technologies, monolithic 3DIC (M3DIC) [2-4], which sequentially fabricates multiple active layers with monolithic inter-tier-vias (MIVs), has power, performance, and cost advantages in comparison to 3DICs based on through-silicon-via (TSV) [5]. Owing to the success of low-temperature processes such as CoolCube TM integration [6] for top-tier transistors in M3DIC, the performance of bottom-tier transistors is less degraded, and thus M3DIC enables nanoscale MIV to be used for connecting vertical transistor/circuit layers [7-10]. To solve the difficulties in filling a high-aspect-ratio MIV, increasing the power density, and reducing the RC delay, a thin interlayer dielectric (ILD) between stacked transistors is created [11]. The electrical coupling between stacked transistors has been investigated because the change in the gate voltage of the bottom-tier transistor affects the current of the top-tier transistor owing to the thinned ILD [12-14].

In 2D planar logic gates, the inverter structure is used as a basic unit cell for the standard cells. In a standard cell, all n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs) or p-type MOSFETs are at one level, where a drain or source is commonly applied. All standard cells are equal in height and can easily fit into a standard row of cells. It is well known that the standard cell layout of a 2D planar logic gate reduces the cell area and makes it easy for the automatic place and route (APR) tool to place and route them [15]. Fig. 1(a) shows a cross-sectional view of a previously reported M3D-NAND gate consisting of a monolithic 3D (M3D) inverter (M3D-INV) used as a basic unit cell, similar to a 2D standard cell [7-9, 12-14]. Because the M3D-NAND gate shares the drain or source regions in top- or bottom-tier transistors, its area and RC delay may be reduced in comparison to those of the NAND gate in which an M3D-INV is used as a basic unit cell and then constructed using interconnects such as metal lines (MLs) or MIVs between M3D-INVs. However, because each standard cell must be designed with its own layout as an example of an M3D-NAND, it requires its own mask. Without designing all layouts of the logic gates separately, only one building block (unit cell), such as an M3D-INV, is needed; thus, one mask is required, which can be uniformly placed by arranging the cells throughout, as shown in Fig. 1(b), and the placed cells can be routed using the interconnects. It is necessary to compare the two types of 3D standard cell methods in terms of their area, power, and delay. In addition, in two types of M3DIC 3D standard cells, the electrical coupling between transistors stacked in an M3D-INV needs to be efficiently simulated and designed for achieving digital logic.

Figure 1. Cross-section of M3D-NAND: (a) previous [8] and (b) proposed versions consisting of modularized inverters.

In this study, various types of logic circuits consisting only of M3D-INVs and connected with interconnects are proposed. In Section II, two types of standard M3D-NAND cell are compared in terms of area, power, and delay. In Section III, the performances of various types of logic circuits consisting of the proposed M3D-INV unit cell are compared according to the thickness of the ILD (TILD). Finally, in Section IV, some concluding remarks are provided.

II. PROPOSED M3D LOGIC GATES

In this section, the previous and proposed M3D-NAND and M3D-NOR gates are compared with results simulated using the technology computer-aided design (TCAD) simulator ATLAS [16].

Fig. 1(a) shows a cross-section of the M3D-NAND gate, similar to a 2D standard cell, which was designed to minimize the area in previous studies [12]. Fig. 1(b) shows a cross section of the NAND gate designed using modularized M3D-INVs, as demonstrated in this study. The top and bottom tiers consist of an n-MOSFET and a p-MOSFET, respectively. The M3D-NAND gate consists of two modularized inverters. The doping concentrations of the source, drain, lightly doped drain (LDD), and channel of the MOSFETs were 1021, 1018, and 1015 cm-3, respectively. The gate length, gate oxide thickness, and TILD of the MOSFETs were 30, 1, and 10 nm, respectively. In addition, SiO2 was used as the gate oxide and ILD. According to the generally used design rule, the distance between the modularized inverters is 50 nm.

Figs. 2(a) and (c) show the structures of the proposed and previous M3D-NAND gates, respectively. The proposed M3D-NAND gates consist of two modularized unit cell M3D-INVs. Figs. 2(b) and (d) show the 2D layouts of the proposed and previous M3D-NAND gates, respectively. The external parasitic capacitances of the M3D-NAND gates shown in Figs. 2(a) and (c) from the MLs, vias, and contacts were extracted using a TCAD simulator [16, 17] and are listed in Table 1, where TILD is divided into 10 and 100 nm units to investigate the electrical coupling effects between stacked transistors.

Table 1 . Extracted capacitance of M3D-NAND.

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns3.444.23CgAns3.474.32
CgBd292.2310.40CgAnd9.2710.23
CgBps1.421.42CgAps0.400.40
Cnsd1.661.94Cpsd0.320.35
Cnsps0.710.09Ccd0.981.00
CgBc1.351.31CgAc2.092.09
Cnsc0.800.87Cpsc0.790.77


Figure 2. (a) Proposed M3D-NAND, (b) 2D layout of proposed M3D-NAND, (c) previous M3D-NAND, and (d) 2D layout of previous M3D-NAND.

Figs. 3(a) and (c) show the structures of the proposed and previous M3D-NOR gates, respectively. The proposed M3D-NOR gates consist of two modularized unit-cell M3D-INVs. Figs. 3(b) and (d) show the 2D layouts of the proposed and previous M3D-NOR gates, respectively. The external parasitic capacitances of the M3D-NOR gates, shown in Figs. 3(a) and (c), from the MLs, vias, and contacts were extracted using the TCAD simulator and are listed in Table 2 for TILD = 10 and 100 nm.

Table 2 . Extracted capacitance of M3D-NOR.

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns1.2613.48CgAns1.7917.95
CgBd17.3010.31CgAnd142.70142.72
CgBps2.7840.37CgAps7.500.65
Cnsd2.4224.20Cpsd3.503.22
Cnsps36.500.19Ccd7.207.00
CgBc2.8936.20CgAc37.5037.41
Cnsc7.807.54Cpsc8.904.37


Figure 3. (a) Proposed M3D-NOR, (b) 2D layout of proposed M3D-NOR, (c) previous M3D-NOR, and (d) 2D layout of previous M3D-NOR.

Figs. 4(a) and (b) show the voltage transfer characteristics (VTCs) and transient responses of the two types of M3D-NAND with TILD = 10 nm, respectively. The M3D-NANDs neglect the MIVs and MLs, as shown in Figs. 2(a) and (c). In Fig. 4(a), the red and blue dotted triangles denote the VTCs of the proposed and previous M3D-NAND gates when VB = 1 V (high level), respectively, and the black lines and symbols denote the VTCs of the proposed and previous M3D-NAND gates when VB = 0 V (low level). The VTCs of the proposed M3D-NAND reproduce those of the previous version well. In Fig. 4(b), the black, red, blue, and red lines denote the inputs VIN,A and VIN,B, output Vout of the proposed M3D-NAND, and output Vout of the previous M3D-NAND, respectively. The extracted propagation delay (tp), falling time (tf), and rising time (tr) of the proposed M3D-NAND increased by 16.4%, 36.1%, and 11.8%, respectively, compared to those of the previous M3D-NAND.

Figure 4. M3D-NAND gate neglecting external parasitic capacitances: (a) VTCs and (b) transient response.

III. SIMULATION RESULTS

In this section, the simulation results of the previous and proposed M3D logics are described using the Simulation Program with Integrated Circuit Emphasis (SPICE) with the extracted parameters of the LETI-UTSOI MOSFET (version 2.1) model for NMOS and PMOS [18], and the extracted external capacitances shown in Tables 1 and 2. The M3D logic considers MIVs and MLs, as shown in Figs. 2 and 3. The area, propagation delay, and power consumption of M3D logic, such as the buffer, NAND, NOR, 2 ´ 1 multiplexer (MUX), and D flip-flop are compared for two cases (TILD = 10 and 100 nm) with and without an electrical coupling between the stacked devices.

Figs. 5(a)-(d) show the transient response of the M3D-NAND, M3D-NOR, M3D 2 × 1 MUX, and M3D D flip-flop, respectively. In Figs. 5(a)-(c), the black and red lines denote the inputs VIN,A and VIN,B, respectively. In Fig. 5(c), the orange line denotes the selection line Vsel for the M3D 2 ´ 1 MUX. In Fig. 5(d), the black and red lines denote clock VClk and input VD of the M3D D flip-flop, respectively. The blue and green lines denote the output Vouts for TILD = 10 and 100 nm, respectively.

Figure 5. Transient response. (a) M3D-NAND gate, (b) M3D-NOR gate, (c) M3D 2x1 MUX, (d) M3D D flip-flop.

Tables 3-5 show the area, propagation delay (tp), rising time (tr), falling time (tf), static power consumption, and dynamic power consumption of the M3D-NAND, M3D-NOR, and three logics of the M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop, respectively. In the case of TILD = 10 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 12%, 15%, 11%, 0%, and 11%, respectively, compared with those of the previous versions. In the case of TILD = 100 nm, the average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-NAND and M3D-NOR increased by approximately 33%, 19%, 13%, 10%, 0%, and 19% compared to those of previous versions, respectively. The average area, propagation delay, rising time, falling time, static power, and dynamic power of the proposed M3D-buffer, M3D 2 ´ 1 MUX, and M3D D flip-flop are the same as those of the previous versions because both consist of modularized M3DINVs. The propagation delay, rising time, falling time, and dynamic power of the proposed M3D logic with TILD = 10 nm increased by 15%, 13%, 14%, and 32% in comparison to those with TILD = 100 nm, respectively. The static power of the proposed M3D logic with TILD = 10 nm decreased by 65% compared to that with TILD = 100 nm because the leakage current of the top-tier transistor in M3D logic with TILD = 10 nm is lower than that with TILD = 100 nm owing to the stronger coupling under TILD = 10 nm [12].

Table 3 . Performance of M3D-NAND gate.

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.834.986.726.22
Rising time [ps]6.546.408.257.65
Failing time [ps]7.627.439.068.47
Static power [nW]01.93.971.93.97
Dynamic power [μW]15.212.117.014.3


Table 4 . Performance of M3D-NOR gate.

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.664.666.145.25
Rising time [ps]13.211.413.812.2
Failing time [ps]2.522.232.612.38
Static power [nW]9.7837.99.7837.9
Dynamic power [μW]15.412.017.014.3


Table 5 . Performance of M3D-buffer, 2x1 MUX, and D flip-flop.

PerformanceM3D-BufferM3D 2x1 MUXM3D D flip-flop
TILD [nm]
101001010010100
Area [nm2]0.160.160.250.250.490.49
Propagation delay [ps]8.066.193.813.27162.0158.5
Rising time [ps]8.257.907.296.027.956.80
Failing time [ps]5.905.445.954.876.265.10
Static power [nW]10.124.14.8918.919.861.2
Dynamic power [μW]35.827.23.612.749.425.98

IV. CONCLUSION

In this study, various types of M3D logic circuits consisting only of modularized M3D-INVs and their interconnects were proposed. The proposed M3D logics were compared with previous M3D logics using TCAD and SPICE simulations. The DC characteristics of the previous and proposed M3D logic systems are almost the same. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. In particular, the average area of the proposed M3D NAND and NOR increased by approximately 37% compared with the previous versions. Although the proposed M3D logic has the disadvantages of a larger space and lower performance than the previous cases, it can be easily designed using a single modularized M3D-INV without designing all layouts of the logic gates separately. The proposed M3D logic gates may be less sensitive to process variations, such as a random dopant fluctuation (RDF) and work function variation because there is no common region between transistors in the logic gates and because the transistors are separated inside their logics. To compare the electrical coupling between the stacked devices in the previous and proposed M3D logic, two cases of TILD = 10 and 100 nm were simulated. The delay and dynamic power consumption of both M3D logics at TILD = 100 nm, in which electrical coupling can be neglected, are faster and lower, respectively, than those at TILD = 10 nm, in which electrical coupling must be considered.

ACKNOWLEDGEMENTS

This research was supported by the Basic Science Research Program through the NRF of Korea, funded by the Ministry of Education (NRF-2019R1A2C1085295). This study was also supported by the IDEC (EDA tool).

Fig 1.

Figure 1.Cross-section of M3D-NAND: (a) previous [8] and (b) proposed versions consisting of modularized inverters.
Journal of Information and Communication Convergence Engineering 2022; 20: 137-142https://doi.org/10.6109/jicce.2022.20.2.137

Fig 2.

Figure 2.(a) Proposed M3D-NAND, (b) 2D layout of proposed M3D-NAND, (c) previous M3D-NAND, and (d) 2D layout of previous M3D-NAND.
Journal of Information and Communication Convergence Engineering 2022; 20: 137-142https://doi.org/10.6109/jicce.2022.20.2.137

Fig 3.

Figure 3.(a) Proposed M3D-NOR, (b) 2D layout of proposed M3D-NOR, (c) previous M3D-NOR, and (d) 2D layout of previous M3D-NOR.
Journal of Information and Communication Convergence Engineering 2022; 20: 137-142https://doi.org/10.6109/jicce.2022.20.2.137

Fig 4.

Figure 4.M3D-NAND gate neglecting external parasitic capacitances: (a) VTCs and (b) transient response.
Journal of Information and Communication Convergence Engineering 2022; 20: 137-142https://doi.org/10.6109/jicce.2022.20.2.137

Fig 5.

Figure 5.Transient response. (a) M3D-NAND gate, (b) M3D-NOR gate, (c) M3D 2x1 MUX, (d) M3D D flip-flop.
Journal of Information and Communication Convergence Engineering 2022; 20: 137-142https://doi.org/10.6109/jicce.2022.20.2.137

Table 1 . Extracted capacitance of M3D-NAND.

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns3.444.23CgAns3.474.32
CgBd292.2310.40CgAnd9.2710.23
CgBps1.421.42CgAps0.400.40
Cnsd1.661.94Cpsd0.320.35
Cnsps0.710.09Ccd0.981.00
CgBc1.351.31CgAc2.092.09
Cnsc0.800.87Cpsc0.790.77

Table 2 . Extracted capacitance of M3D-NOR.

Capacit anceTILD [nm]Capacit anceTILD [nm]
1010010100
Values [aF]Values [aF]
CgBns1.2613.48CgAns1.7917.95
CgBd17.3010.31CgAnd142.70142.72
CgBps2.7840.37CgAps7.500.65
Cnsd2.4224.20Cpsd3.503.22
Cnsps36.500.19Ccd7.207.00
CgBc2.8936.20CgAc37.5037.41
Cnsc7.807.54Cpsc8.904.37

Table 3 . Performance of M3D-NAND gate.

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.834.986.726.22
Rising time [ps]6.546.408.257.65
Failing time [ps]7.627.439.068.47
Static power [nW]01.93.971.93.97
Dynamic power [μW]15.212.117.014.3

Table 4 . Performance of M3D-NOR gate.

PerformancePreviousProposed
TILD [nm]
1010010100
Area [nm2]0.120.120.160.16
Propagation delay [ps]5.664.666.145.25
Rising time [ps]13.211.413.812.2
Failing time [ps]2.522.232.612.38
Static power [nW]9.7837.99.7837.9
Dynamic power [μW]15.412.017.014.3

Table 5 . Performance of M3D-buffer, 2x1 MUX, and D flip-flop.

PerformanceM3D-BufferM3D 2x1 MUXM3D D flip-flop
TILD [nm]
101001010010100
Area [nm2]0.160.160.250.250.490.49
Propagation delay [ps]8.066.193.813.27162.0158.5
Rising time [ps]8.257.907.296.027.956.80
Failing time [ps]5.905.445.954.876.265.10
Static power [nW]10.124.14.8918.919.861.2
Dynamic power [μW]35.827.23.612.749.425.98

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JICCE
Sep 30, 2022 Vol.20 No.3, pp. 143~233

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