The Korea Institute of Information and Commucation Engineering 2008; 6(1): 29-33
Published online March 31, 2008
© Korea Institute of Information and Communication Engineering
This paper presents the proposal and hardware design of JPEG baseline encoder. The JPEG encoder system consists of line buffer, 2-D DCT, quantization, entropy encoding, and packer. A fully pipelined scheme for JPEG encoder is adopted to speed-up an image compression. The proposed architecture was described in VHDL and synthesized in Xilinx ISE 7.1i and simulated by modelsim 6.1i. The results showed that the performance of the designed JPEG baseline encoder is higher than that demanded by real-time applications for
Keywords JPEG,Baseline,Encoder,Compression,Pipeline Method,Entropy Encoder,2-D DCT,Image
The Korea Institute of Information and Commucation Engineering 2008; 6(1): 29-33
Published online March 31, 2008
Copyright © Korea Institute of Information and Communication Engineering.
Kim, Kyung-Hyun;Sonh, Seung-Il;
Department of Information and Communications, Hanshin University, Department of Information and Communications, Hanshin University
This paper presents the proposal and hardware design of JPEG baseline encoder. The JPEG encoder system consists of line buffer, 2-D DCT, quantization, entropy encoding, and packer. A fully pipelined scheme for JPEG encoder is adopted to speed-up an image compression. The proposed architecture was described in VHDL and synthesized in Xilinx ISE 7.1i and simulated by modelsim 6.1i. The results showed that the performance of the designed JPEG baseline encoder is higher than that demanded by real-time applications for
Keywords: JPEG,Baseline,Encoder,Compression,Pipeline Method,Entropy Encoder,2-D DCT,Image